BER-optimal analog-to-digital converters for communication links
BER-optimal analog-to-digital converters for communication links
复制标题
用于通信链路的 BER 优化模数转换器
DOI：
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发表时间：
2012
期刊：
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通讯作者：
A. Singer
中科院分区：
文献类型：
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作者：
R. Narasimha;Minwei Lu;Naresh R Shanbhag;A. Singer
在本文中，我们提出了误码率最优的模数转换器(ADC)，其中量化级别和阈值被非均匀地设置以最小化误比特率(BER)。这与当今充当透明波形保持器的ADC形成了鲜明对比。对不同通信信道的仿真结果表明，该ADC具有较高的整形增益，在码间干扰(ISI)较低的信道上可获得2.5dB的成形增益，而在符号间干扰(ISI)较高的信道上可达到30dB以上的成形增益。此外，3位误码率最优ADC的误码率与4位均匀ADC相同，甚至更低。对于闪存转换器，这相当于功率降低2倍。与误码率最优ADC兼容的基于查找表的均衡器在45 nm CMOS工艺中可将功耗降低高达47%，面积降低高达66%。由误码率最优的ADC产生的成形增益可用于降低发射机的峰值传输摆幅或降低ADC的功耗。
In this paper, we propose BER-optimal analog-to-digital converters (ADC) where quantization levels and thresholds are set non-uniformly to minimize the bit-error rate (BER). This is in contrast to present-day ADCs which act as transparent waveform preservers. Simulations for various communication channels show that the BER-optimal ADC achieves shaping gains that range from 2.5dB for channels with low intersymbol interference (ISI) to more than 30dB for channels with high ISI. Moreover, a 3-bit BER-optimal ADC achieves the same or even lower BER than a 4-bit uniform ADC. For flash converters, this corresponds a power reduction by 2×. Look-up table based equalizers compatible with BER-optimal ADCs are shown to reduce the power up to 47% and the area up to 66% in a 45nm CMOS process. The shaping gain due to BER-optimal ADCs can be exploited to lower peak transmit swings at the transmitter or decrease power consumption of the ADC.