IP Cores for Graph Kernels on FPGAs
IP Cores for Graph Kernels on FPGAs
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DOI：
10.1109/hpec.2019.8916363
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发表时间：
2019-09
期刊：
影响因子：
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通讯作者：
S. Kuppannagari;Rachit Rajat;R. Kannan;A. Dasu;V. Prasanna
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作者：
S. Kuppannagari;Rachit Rajat;R. Kannan;A. Dasu;V. Prasanna
图形是在许多现实世界中代表网络数据的强大抽象，使大规模的图形分析的需求导致宽度采用专用的硬件加速器（例如FPGA）在此目的中，我们开发了IP核心。非重叠分区改进芯片数据重复使用，以利用内部和分间的并行访问，并讨论了带有各种顶点属性的FPGA设计针对平台由大型的外部DDR4存储器存储图形数据和Intel Stratix FPGA加速过程，我们的加速器可维持高达2250、2300、3378和2.178亿的高吞吐量。 20.5×SPMV的速度，PR的16.4×速度，SSSP的3.5×速度和WCC的35.1×加速度，并且与两个最先进的FPGA框架相比，我们的设计表现出高达5.3×spmv的速度，然后绩效为1.64×速度。假设该图存储在HBM2而不是DRAM。
Graphs are a powerful abstraction for representing networked data in many real-world applications. The need for performing large scale graph analytics has led to widespread adoption of dedicated hardware accelerators such as FPGA for this purpose. In this work, we develop IP cores for several key graph kernels. Our IP cores use graph processing over partitions (GPOP) programming paradigm to perform computations over graph partitions. Partitioning the input graph into nonoverlapping partitions improves on-chip data reuse. Additional optimizations to exploit intra and interpartition parallelism and to reduce external memory accesses are also discussed. We generate FPGA designs for general graph algorithms with various vertex attributes and update propagation functions, such as Sparse Matrix Vector Multiplication (SpMV), PageRank (PR), Single Source Shortest Path (SSSP), and Weakly Connected Component (WCC). We target a platform consisting of large external DDR4 memory to store the graph data and Intel Stratix FPGA to accelerate the processing. Experimental results show that our accelerators sustain a high throughput of up to 2250, 2300, 3378, and 2178 Million Traversed Edges Per Second (MTEPS) for SpMV, PR, SSSP and WCC, respectively. Compared with several highly-optimized multi-core designs, our FPGA framework achieves up to 20.5× speedup for SpMV, 16.4× speedup for PR, 3.5× speedup for SSSP, and 35.1× speedup for WCC, and compared with two state-of-the-art FPGA frameworks, our designs demonstrate up to 5.3× speedup for SpMV, 1.64× speedup for PR, and 1.8× speedup for WCC, respectively. We develop a performance model for our GPOP paradigm. We then perform performance predictions of our designs assuming the graph is stored in HBM2 instead of DRAM. We further discuss extensions to our optimizations to improve the throughput.