Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance
Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance
复制标题
DOI:
10.1109/ted.2007.911034
复制
发表时间:
2008
影响因子:
3.1
通讯作者:
S. Takagi;T. Iisawa;T. Tezuka;T. Numata;S. Nakaharai;N. Hirashita;Y. Moriyama;K. Usuda;E. Toyoda-E
中科院分区:
文献类型:
--
作者:
S. Takagi;T. Iisawa;T. Tezuka;T. Numata;S. Nakaharai;N. Hirashita;Y. Moriyama;K. Usuda;E. Toyoda-E
An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.