Fixed-Latency, Multi-Gigabit Serial Links With Xilinx FPGAs
Fixed-Latency, Multi-Gigabit Serial Links With Xilinx FPGAs
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DOI：
10.1109/tns.2010.2101083
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发表时间：
2011-01
影响因子：
1.8
通讯作者：
R. Giordano;A. Aloisio
中科院分区：
文献类型：
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作者：
R. Giordano;A. Aloisio
大多数现成的高速串行器/解串器 (SerDes) 芯片在复位、失锁或电源周期后无法在数据路径上保持相同的延迟。通常会做出这种实施选择，因为固定延迟操作需要专用电路，而大多数电信和数据玉米应用通常不需要它们。然而，高能物理实验的定时同步应用和触发系统将受益于固定延迟链路。在本文中，我们提出了一种基于 Xilinx Virtex 5 和 Spartan 6 现场可编程门阵列 (FPGA) 中嵌入的高速 SerDeses 的链路架构。我们讨论了架构的延迟性能，并展示了如何使其保持恒定且可预测。我们还提供了测试结果，显示了链路的固定延迟，最后我们提供了一些指导原则，以利用我们的解决方案与其他 SerDes 设备。
Most of the off-the-shelf high-speed Serializer-Deserializer (SerDes) chips do not keep the same latency through the data-path after a reset, a loss of lock or a power cycle. This implementation choice is often made because fixed-latency operations require dedicated circuitry and they are usually not needed for most telecom and data-corn applications. However timing synchronization applications and triggers systems of the high energy physics experiments would benefit from fixed-latency links. In this paper, we present a link architecture based on the highspeed SerDeses embedded in Xilinx Virtex 5 and Spartan 6 Field Programmable Gate Arrays (FPGAs). We discuss the latency performance of our architecture and we show how we made it constant and predictable. We also present test results showing the fixed latency of the link and we finally offer some guidelines to exploit our solution with other SerDes devices.