A 60-GHz Outphasing Transmitter in 40-nm CMOS
A 60-GHz Outphasing Transmitter in 40-nm CMOS
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DOI：
10.1109/jssc.2012.2216692
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发表时间：
2012-12-01
影响因子：
5.4
通讯作者：
Reynaert, Patrick
中科院分区：
文献类型：
--
作者：
Zhao, Dixian;Kulkarni, Shailesh;Reynaert, Patrick
本文介绍了一种基于40nm CMOS的60ghz同相发射机的分析、设计和实现。60ghz同相发射机在保持足够的线性度的同时，优化了高输出功率和峰值功率附加效率（PAE）。该芯片的有效面积为0.33 mm(2)，在1 v电源电压下消耗217 mW，提供15.6 dbm线性输出功率，PAE （PA）为25%。它实现了500 mb /s的16QAM调制，平均输出功率为12.5 dbm，平均效率（PA）为15%，EVM为-22 dB。采用失配补偿和相位校正后，平均输出功率和效率分别提高了约1.6 dB和4%。
This paper presents the analysis, design, and implementation of a 60-GHz outphasing transmitter in 40-nm bulk CMOS. The 60-GHz outphasing transmitter is optimized for high output power and peak power-added efficiency (PAE) while maintaining sufficient linearity. The chip occupies an active area of 0.33 mm(2) and consumes 217 mW from a 1-V supply voltage, delivering 15.6-dBm linear output power with 25% PAE (PA). It achieves a 500-Mb/s 16QAM modulation with 12.5-dBm average output power and 15% average efficiency (PA) at an EVM of -22 dB. Mismatch compensation and phase correction are applied to further improve the average output power and efficiency by about 1.6 dB and 4%, respectively.