Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL
Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL
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研究面向 OpenCL 的英特尔 FPGA SDK 中自动优化的潜力
DOI：
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发表时间：
2020
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通讯作者：
Rob A. Rutenbar
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作者：
Adel Ejjeh;Vikram S. Adve;Rob A. Rutenbar
高级综合（HLS）工具，如英特尔FPGA SDK for OpenCL，通过提供简单的程序指令（pragmas）和/或API调用，允许硬件程序员使用高级语言（如HLS-C或OpenCL），提高硬件设计生产力并实现高效的设计空间探索。然而，现代HLS工具有时会错过高性能所必需的重要优化。在这张海报中，我们提出了一个在HLS优化的权衡研究，和一个现代的HLS工具在自动优化应用程序的潜力。我们使用面向OpenCL的英特尔FPGA SDK和Arria 10 FPGA开发套件，在通用的5级相机ISP流水线上进行研究。我们表明，在HLS工具中的自动优化是有价值的，实现高达2.7倍的加速比相当于CPU执行。然而，通过进一步的手动调优，我们可以在CPU上实现高达36.5倍的加速。我们得出了几个具体的经验教训，由简单的指令指导的自动优化的有效性和高性能所需的手动重写的性质。最后，我们得出的结论是，HLS工具当前的潜力存在差距，需要通过下一代研究来填补。
High Level Synthesis (HLS) tools, like the Intel FPGA SDK for OpenCL, improve hardware design productivity and enable efficient design space exploration, by providing simple program directives (pragmas) and/or API calls that allow hardware programmers to use higher-level languages (like HLS-C or OpenCL). However, modern HLS tools sometimes miss important optimizations that are necessary for high performance. In this poster, we present a study of the tradeoffs in HLS optimizations, and the potential of a modern HLS tool in automatically optimizing an application. We perform the study on a generic, 5-stage camera ISP pipeline using the Intel FPGA SDK for OpenCL and an Arria 10 FPGA Dev Kit. We show that automatic optimizations in the HLS tool are valuable, achieving up to 2.7x speedup over equivalent CPU execution. With further hand tuning, however, we can achieve up to 36.5x speedup over CPU. We draw several specific lessons about the effectiveness of automatic optimizations guided by simple directives and about the nature of manual rewriting required for high performance. Finally, we conclude that there is a gap in the current potential of HLS tools which needs to be filled by next-gen research.