A Hybrid Logic Simulator Using LUT Cascade Emulators
A Hybrid Logic Simulator Using LUT Cascade Emulators
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发表时间：
2007
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通讯作者：
Hiroki Nakahara;Tsutomu Sasao;M. Matsuura
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作者：
Hiroki Nakahara;Tsutomu Sasao;M. Matsuura
本文提出了一种事件驱动和基于循环的混合逻辑模拟器。对于存储器和三态缓冲器等特殊原语，它使用事件驱动方法。对于其他部分，它使用基于循环的方法，使用LUT级联仿真器。为了模拟大规模电路，该方法将电路划分为若干小的单元，每个单元用LUT级联仿真器实现。接下来，它通过互连来组合这些仿真器。由于乘法器通常需要LUT级联中的大存储器，因此使用处理器的指令而不是LUT级联。这将减少代码大小和模拟时间。实验结果表明，该方法对含有算术运算的电路是有效的。
This paper presents a hybrid logic simulator using both an event-driven and a cycle-based methods. For special primitives such as memories and tri-state buffers, it uses an event-driven method. For other parts, it uses a cyclebased method using LUT cascade emulators. To simulate a large scale circuit, it partitions the circuit into smaller ones, and realizes each part by an LUT cascade emulator. Next, it combines these emulators by interconnections. Since a multiplier often requires large memories in an LUT cascade, an instruction of the processor is used instead of the LUT cascade. This will reduce the code size and the simulation time. Our experiment shows that proposed method is effective for circuits including arithmetic operations.