A Single-Clock-Phase Sense Amplifier Architecture with 9x Smaller Clock-to-Q Delay Compared to the StrongARM & 6.3dB Lower Noise Compared to Double-Tail

A Single-Clock-Phase Sense Amplifier Architecture with 9x Smaller Clock-to-Q Delay Compared to the StrongARM & 6.3dB Lower Noise Compared to Double-Tail
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与 StrongARM 相比,单时钟相检测放大器架构的时钟至 Q 延迟小 9 倍

DOI:
10.1109/vlsitechnologyandcir46769.2022.9830355
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发表时间:
2022
期刊:
International Symposium on VLSI Technology Systems and Application
影响因子:
--
通讯作者:
Anand, T.
Anand, T.
中科院分区:
--
文献类型:
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作者:
Lin, X.;Megahed, M.;Anand, T.

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