Dynamic voltage scaling for commercial FPGAs
Dynamic voltage scaling for commercial FPGAs
复制标题
商用 FPGA 的动态电压调节
DOI：
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复制
发表时间：
2005
期刊：
影响因子：
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通讯作者：
S. Wilton
中科院分区：
文献类型：
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作者：
G. C. Chow;L. S. M. Tsui;P. Leong;W. Luk;S. Wilton
描述了一种在商用fpga上支持动态电压缩放（DVS）的方法。逻辑延迟测量电路（LDMC）用于确定逆变器链在运行时的各种运行条件下的速度。然后选择一个期望的LDMC值，该值旨在匹配工作电路的关键路径和安全裕度；采用闭环控制方案，通过自动调节施加到FPGA上的电压，在芯片温度变化时保持所需的LDMC值。我们描述了在不同时钟频率和温度下的各种电路上使用该技术的实验，以证明其实用性和鲁棒性。可以观察到，VINT电源可以节省4%到54%的电力
A methodology for supporting dynamic voltage scaling (DVS) on commercial FPGAs is described. A logic delay measurement circuit (LDMC) is used to determine the speed of an inverter chain for various operating conditions at run time. A desired LDMC value, intended to match the critical path of the operating circuit plus a safety margin, is then chosen; a closed loop control scheme is used to maintain the desired LDMC value as chip temperature changes, by automatically adjusting the voltage applied to the FPGA. We describe experiments using this technique on various circuits at different clock frequencies and temperatures to demonstrate its utility and robustness. Power savings between 4% and 54% for the VINT supply are observed