Thermodynamic-RAM technology stack
Thermodynamic-RAM technology stack
复制标题
DOI：
10.1080/17445760.2017.1314472
复制
发表时间：
2018-01-01
影响因子：
1.1
通讯作者：
Molter, Timothy W.
中科院分区：
文献类型：
--
作者：
Nugent, M. Alexander;Molter, Timothy W.
We introduce a technology stack or specification describing the multiple levels of abstraction and specialisation needed to implement a neuromorphic processor (NPU) based on the previously-described concept of AHaH Computing and integrate it into today's digital computing systems. The general purpose NPU implementation described here is called Thermodynamic-RAM (kT-RAM) and is just one of many possible architectures, each with varying advantages and trade offs. Bringing us closer to brain-like neural computation, kT-RAM will provide a general-purpose adaptive hardware resource to existing computing platforms enabling fast and low-power machine learning capabilities that are currently hampered by the separation of memory and processing, a.k.a the von Neumann bottleneck. Because understanding such a processor based on non-traditional principles can be difficult, by presenting the various levels of the stack from the bottom up, layer by layer, explaining kT-RAM becomes a much easier task. The levels of the Thermodynamic-RAM technology stack include the memristor, synapse, AHaH node, kT-RAM, instruction set, sparse spike encoding, kT-RAM emulator, and SENSE server.[GRAPHICS]The Thermodynamic RAM (kT-RAM) technical stack defines a specification for building a neuromorphic processor based on AHaH computing, a self-organizing attractor-based computing principle. Unlike a von Neumann digital architecture where memory is physically separated from processor, the memristor can be used for both memory and processor at the same time, much like in biological brains. This basic building block can be paired to create a synapse, several synapses can be combined to create a linear neuron, and several neurons can be spread out across a core. This adaptive analog resource can be integrated into existing hardware and software platforms as a co-processor for machine learning applications via a digital I/O interface and instructions set.
