Back side exposure of variable size through silicon vias
Back side exposure of variable size through silicon vias
复制标题
通过硅通孔进行可变尺寸的背面曝光
DOI：
10.1116/1.2221313
复制
发表时间：
2006
影响因子：
1.4
通讯作者：
L. Schaper
中科院分区：
文献类型：
--
作者：
T. Rowbotham;J. Patel;T. Lam;I. Abhulimen;S. Burkett;L. Cai;L. Schaper
微尺度垂直互连的形成使得芯片堆叠应用的三维互连成为可能。这些垂直互连或金属填充的硅通孔是通过一系列处理步骤形成的，这些处理步骤包括硅蚀刻、绝缘/阻挡层/晶种沉积、电镀Cu以填充通孔、晶片研磨和减薄以及用于接触的背面处理。位于同一晶片中的可变直径尺寸通孔允许许多应用的集成灵活性。在单个晶片上生产可变尺寸的硅通孔（VTSV）是具有挑战性的。本文介绍了有关使用独特的晶圆背面处理技术的VTSV曝光的细节。通孔直径在10-30μm的范围内，并且由于通常观察到的反应离子蚀刻滞后，蚀刻深度随通孔直径而变化。在这种方法中，成品晶圆比以前项目中生产的晶圆更厚，这降低了剥离过程中晶圆断裂的风险。
The formation of microscale vertical interconnects enables three-dimensional interconnects for chip stacking applications. These vertical interconnects, or metal filled through silicon vias, are formed by a series of processing steps that include silicon etch, insulation/barrier/seed deposition, electroplated Cu to fill via, wafer grinding and thinning, and back side processing for contacts. Variable diameter size vias residing in the same wafer allow flexibility in integration for many applications. Producing variable size through silicon vias (VTSVs) on a single wafer is challenging. This article presents details regarding the exposure of VTSV using a unique wafer back side processing technique. Via diameters are in the range of 10–30μm and etch depth varies with via diameter due to the commonly observed reactive ion etch lag. In this approach, the finished wafers are thicker than that produced in a previous project which reduces the risk of wafer breakage during the debonding process.