RTL-to-GDS Design Tools for Monolithic 3D ICs
RTL-to-GDS Design Tools for Monolithic 3D ICs
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适用于单片 3D IC 的 RTL 至 GDS 设计工具
DOI：
10.1145/3400302.3415780
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
S. Lim
中科院分区：
文献类型：
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作者：
Jinwoo Kim;Gauthaman Murali;Pruek Vanna;Edward Lee;Daehyun Kim;Arjun Chaudhuri;Sanmitra Banerjee;K. Chakrabarty;S. Mukhopadhyay;S. Lim
在本文中，我们提出了RTL到GDS设计流程的单片3D集成电路（M3 D）内置碳纳米管场效应晶体管和电阻存储器。我们的工具流程基于商业2D工具和智能方法，可将其扩展到进行M3 D设计和仿真。我们提供了一个后布线优化流程，它充分利用了底层M3 D工艺设计套件（PDK）的潜力，以实现功耗、性能和面积（PPA）优化。我们还对M3 D设计进行IR压降和热分析，以提高可靠性。为了提高M3 D设计的可测性，我们开发了可测性设计（DFT）方法，并在设计中集成了低开销的内置自测模块，用于测试层间过孔（ILV）以及各层中的逻辑电路。我们的基准设计是RISC-V Rocketcore，这是一款开源处理器。我们的实验表明，8.1%的功率，19.6%的线长和55.7%的面积节省与M3 D设计相比，在等性能。此外，我们的IR压降和热分析表明，我们的M3 D设计具有可接受的功率和热完整性。
In this paper, we propose RTL-to-GDS design flow for monolithic 3D ICs (M3D) built with carbon nanotube field-effect transistors and resistive memory. Our tool flow is based on commercial 2D tools and smart ways to extend them to conduct M3D design and simulation. We provide a post-route optimization flow, which exploits the full potential of the underlying M3D process design kit (PDK) for power, performance and area (PPA) optimization. We also conduct IR-drop and thermal analysis on M3D designs to improve the reliability. To enhance the testability of our M3D designs, we develop design-for-test (DFT) methodologies and integrate a low-overhead built-in self-test module into our design for testing inter-layer vias (ILVs) as well as logic circuitries in the individual tiers. Our benchmark design is RISC-V Rocketcore, which is an open source processor. Our experiments show 8.1% of power, 19.6% of wirelength and 55.7% of area savings with M3D designs at iso-performance compared to its 2D counterpart. In addition, our IR-drop and thermal analyses indicate acceptable power and thermal integrity in our M3D design.