A code compression system based on pipelined interpreters
A code compression system based on pipelined interpreters
复制标题
基于流水线解释器的代码压缩系统
DOI：
10.1002/(sici)1097-024x(199909)29:11
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发表时间：
1999
期刊：
影响因子：
--
通讯作者：
R. Wiel
中科院分区：
文献类型：
--
作者：
J. Hoogerbrugge;L. Augusteijn;Jeroen Trum;R. Wiel
本文描述了一个用于压缩代码生成的系统。在高度优化的解释器上执行的系统通过与常用基本指令的模式相对应的高度结构。 Philips Trimedia VLIW处理器被管道上的解释速度。从内存中获取，在三个周期的载荷潜伏期和四个周期的跳跃潜伏期中，解释器每指示达到四个周期的峰值性能描述了每个指令的持续性能。分别。版权所有©1999 John Wiley＆Sons，Ltd。
This paper describes a system for compressed code generation. The code of applications is partioned into time‐critical and non‐time‐critical code. Critical code is compiled to native code, and non‐critical code is compiled to a very dense virtual instruction set which is executed on a highly optimized interpreter. The system employs dictionary‐based compression by means of superinstructions which correspond to patterns of frequently used base instructions. The code compression system is designed for the Philips TriMedia VLIW processor. The interpreter is pipelined to achieve a high interpretation speed. The pipeline consists of three stages: fetch, decode, and execute. While one instruction is being executed, the next instruction is decoded, and the next one after that is fetched from memory. On a TriMedia VLIW with a load latency of three cycles and a jump latency of four cycles, the interpreter achieves a peak performance of four cycles per instruction and a sustained performance of 6.27 cycles per instruction. Experiments are described that demonstrate the compression quality of the system and the execution speed of the pipelined interpreter; these were found to be about five times more compact than native TriMedia code and a slowdown of about eight times, respectively. Copyright © 1999 John Wiley & Sons, Ltd.