A reconfigurable VLSI coprocessing system for the block matching algorithm
A reconfigurable VLSI coprocessing system for the block matching algorithm
复制标题
用于块匹配算法的可重构VLSI协处理系统
DOI：
10.1109/92.609876
复制
发表时间：
1997
期刊：
影响因子：
--
通讯作者：
W. Yang
中科院分区：
文献类型：
--
作者：
A. Bugeja;W. Yang
由于全搜索块匹配算法的计算和I/O密集型特性以及在各种计算机视觉和图像处理应用中的重要性，近年来已经提出了几种用于全搜索块匹配算法的VLSI结构。提出了一种新的适合与通用微处理器集成的粗粒度可重构协处理器。180000晶体管定制VLSI设计在4.12min/spl次/2.59 mm管芯上实现，并已经过高达33 MHz的全面测试。对于一个典型的图像数据库搜索应用程序，一个由4个协处理器组成的样本系统通过33MHzPCI总线接口，在运行完全优化的汇编代码的80486 MHzDX2/66Mhz和150MHzPentium上将提供320SPL倍/SPL和150MHzPentium/SPL倍/的加速比。
Several VLSI architectures for the full-search block matching algorithm have been proposed in recent years due to its computation and I/O-intensive nature and its importance in various computer vision and image processing applications. This paper presents a new coarse grained reconfigurable coprocessor which is suitable for integration with general purpose microprocessors. The 180000 transistor custom VLSI design was implemented in 0.6 /spl mu/m CMOS on a 4.12 min/spl times/2.59 mm die and has been fully tested up to 33 MHz. For a typical image database search application, a sample system consisting of four coprocessors interfaced through a 33 MHz PCI bus will provide a speedup of 320/spl times/ over an 80486 DX2/66 MHz and 64/spl times/ over a 150-MHz Pentium running fully optimized assembly code.