A Hybrid Filtering Technique-Based PLL Targeting Fast and Robust Tracking Performance under Distorted Grid Conditions
A Hybrid Filtering Technique-Based PLL Targeting Fast and Robust Tracking Performance under Distorted Grid Conditions
复制标题
基于混合滤波技术的 PLL，旨在在网格畸变条件下实现快速、鲁棒的跟踪性能
DOI：
10.3390/en11040973
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发表时间：
2018-04-01
期刊：
影响因子：
3.2
通讯作者：
Ma, Yiming
中科院分区：
文献类型：
--
作者：
Li, Yunlu;Yang, Junyou;Ma, Yiming
在大多数并网电力变流器应用中，由于其实现简单，锁相环（PLL）可能是应用最广泛的电网同步技术。然而，当电网电压处于不平衡和畸变条件下时，其相位跟踪性能往往会变差。许多滤波技术被用于解决这一问题，但却以减慢瞬态响应为代价。对于锁相环来说，在不降低其滤波能力的情况下实现令人满意的动态性能是一项重大挑战。为了应对这一挑战，本文提出了一种混合滤波技术。我们的思路是分别在锁相环的预滤波阶段和内环中消除基频负序（FFNS）和其他谐波序列。二阶广义积分器（SOGI）用于在帕克变换之前去除基频负序。这使得移动平均滤波器（MAF）能够以更窄的窗口长度消除其他谐波，这意味着由移动平均滤波器引起的时间延迟减少了。整个混合滤波技术包含在一个准I型锁相环结构（QT1 - PLL）中，该结构能够提供快速的动态性能。建立了所提出的锁相环的小信号模型。基于该模型，给出了针对快速瞬态响应的参数设计准则。进行了全面的实验以证实我们方法的有效性。结果表明，所提出的锁相环的稳定时间小于一个电网周期，这比大多数广泛应用的锁相环都要短。在额定和不良电网条件下，其谐波抑制能力也优于其他方法。
In most grid-connected power converter applications, the phase-locked loop (PLL) is probably the most widespread grid synchronization technique, owing to its simple implementation. However, its phase-tracking performance tends to worsen when the grid voltage is under unbalanced and distorted conditions. Many filtering techniques are utilized to solve this problem, however, at the cost of slowing down the transient response. It is a major challenge for PLL to achieve a satisfactory dynamic performance without degrading its filtering capability. To tackle this challenge, a hybrid filtering technique is proposed in this paper. Our idea is to eliminate the fundamental frequency negative sequence (FFNS) and other harmonic sequences at the prefiltering stage and inner loop of PLL, respectively. Second-order generalized integrators (SOGIs) are used to remove FFNS before the Park transformation. This makes moving average filters (MAFs) eliminate other harmonics with a narrowed window length, which means the time delay that is caused by MAFs is reduced. The entire hybrid filtering technique is included in a quasi-type-1 PLL structure (QT1-PLL), which can provide a rapid dynamic behavior. The small-signal model of the proposed PLL is established. Based on this model, the parameter design guidelines targeting the fast transient response are given. Comprehensive experiments are carried out to confirm the effectiveness of our method. The results show that the settling time of the proposed PLL is less than one grid cycle, which is shorter than most of the widespread PLLs. The harmonic rejection capability is also better than other methods, under both nominal and adverse grid conditions.