Automatic generation of high throughput energy efficient streaming architectures for arbitrary fixed permutations
Automatic generation of high throughput energy efficient streaming architectures for arbitrary fixed permutations
复制标题
自动生成任意固定排列的高吞吐量节能流架构
DOI：
10.1109/fpl.2015.7293944
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发表时间：
2015
期刊：
影响因子：
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通讯作者：
V. Prasanna
中科院分区：
文献类型：
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作者：
Ren Chen;V. Prasanna
由于其高数据速率和简单的控制，流架构已成为流行的数据密集型应用的硬件实现。设计这种架构的一个关键问题是置换流数据。本文提出了一种在流数据上实现任意固定置换的技术。我们开发了一个参数化的架构，它接受数据流作为输入，并在一定的延迟后生成置换数据。我们的设计以每个周期p的固定速率接受连续输入，其中p是架构的数据并行性。为了构建给定固定排列的流传输架构，我们通过配置经典的Benes网络来开发一种映射方法以获得数据路径和控制逻辑。我们展示了一个完整的设计自动化工具，作为输入的设计参数，包括置换模式和数据并行度p，并产生寄存器传输级Verilog描述的设计。我们评估所产生的设计Xilinx Virtex-7 FPGA使用后的布局和布线结果。
Due to their high data-rate and simple control, streaming architectures have become popular for hardware implementation of data intensive applications. A key problem in designing such architectures is to permute streaming data. In this paper, we present a technique to realize arbitrary fixed permutation on streaming data. We develop a parameterized architecture which accepts data streams as input and generates the permuted data after a certain amount of delay. Our design accepts continuous input at a fixed rate of p per cycle, where p is the data parallelism of the architecture. To construct the streaming architecture for a given fixed permutation, we develop a mapping approach by configuring the classic Benes network to obtain the datapath and the control logic. We demonstrate a complete design automation tool which takes as input design parameters including the permutation pattern and the data parallelism p, and produces register-transfer level Verilog description of the design. We evaluate the generated designs on Xilinx Virtex-7 FPGA using post place-and-route results.