Checkpointing-Aware Loop Tiling for Energy Harvesting Powered Nonvolatile Processors
Checkpointing-Aware Loop Tiling for Energy Harvesting Powered Nonvolatile Processors
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DOI：
10.1109/tcad.2018.2803624
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发表时间：
2019
影响因子：
2.9
通讯作者：
Fuyang Li;Keni Qiu;Mengying Zhao;J. Hu;Yongpan Liu;Yong Guan;C. Xue
中科院分区：
文献类型：
--
作者：
Fuyang Li;Keni Qiu;Mengying Zhao;J. Hu;Yongpan Liu;Yong Guan;C. Xue
As power failures often occur in energy harvesting powered nonvolatile processors (NVPs), checkpointing is needed during program execution. It is observed that checkpointing is implemented with high overhead in applications with loops, because a large amount of data needs backup during loop execution. As such, we are motivated to reduce the amount of checkpointing data by analyzing data locality and shortening data lifetime in loops. This paper proposes a checkpointing-aware loop tiling technique which targets to reduce the checkpointing and recovering overheads for loops. Specifically, we first derive the optimal tile size for nested loops considering checkpointing distance and data dependencies. Then, the implementations of checkpointing and recovering for tiled loops are presented. Finally, the experiments are conducted to evaluate the effectiveness of the proposed method. The experimental results show that compared to the no-tiling method, the checkpointing-aware loop tiling method reduces the checkpointing and recovering data by 36.2% on average and reduces the total execution time and dynamic energy for checkpointing and recovering by 27.2% and 22.9% on average, respectively.
