Systolic-Array Spiking Neural Accelerators with Dynamic Heterogeneous Voltage Regulation

Systolic-Array Spiking Neural Accelerators with Dynamic Heterogeneous Voltage Regulation
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DOI:
10.1109/ijcnn52387.2021.9534037
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发表时间:
2021-07
期刊:
2021 International Joint Conference on Neural Networks (IJCNN)
影响因子:
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通讯作者:
Jeong-Jun Lee;Jianhao Chen;Wenrui Zhang;Peng Li
Jeong-Jun Lee;Jianhao Chen;Wenrui Zhang;Peng Li
中科院分区:
其他
文献类型:
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作者:
Jeong-Jun Lee;Jianhao Chen;Wenrui Zhang;Peng Li

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脉冲神经网络(SNN)是新一代的神经网络,提出了一种大脑启发的事件驱动模型,具有时空信息处理的优势。由于计算密集型神经加速器需要高功耗,因此适当的功率传输网络(PDN)设计是确保功率效率和完整性的关键要求。然而,SNN加速器的PDN设计还没有得到广泛的研究,尽管它在能源效率方面有很大的潜在好处。在本文中,我们提出了第一个研究动态异构电压调节(HVR)的尖峰神经加速器,以最大限度地提高系统的能源效率,同时确保电源的完整性。我们提出了一种新的稀疏工作负载感知的动态PDN控制策略,该策略可以在脉动阵列上实现稀疏尖峰计算的高能效。通过探索PDN控制的尖峰计算的稀疏输入和全或无性质,我们探索了不同类型的PDN,以加速使用动态视觉传感器(DVS)手势数据集训练的尖峰卷积神经网络(S-CNN)。此外,我们展示了各种功率门控方案,以进一步优化所提出的PDN架构,这导致在基于脉动阵列的加速器上尖峰神经计算的总能量开销减少三倍以上。
Spiking neural networks (SNNs) have emerged as a new generation of neural networks, presenting a brain-inspired event-driven model with advantages in spatiotemporal information processing. Due to the need for high power consumption of compute-intensive neural accelerators, adequate power delivery network (PDN) design is a key requirement to ensure power efficiency and integrity. However, PDN design for SNN accelerators has not been extensively studied despite its great potential benefit in energy efficiency. In this paper, we present the first study on dynamic heterogeneous voltage regulation (HVR) for spiking neural accelerators to maximize system energy efficiency while ensuring power integrity. We propose a novel sparse-workload-aware dynamic PDN control policy, which enables high energy efficiency of sparse spiking computation on a systolic array. By exploring sparse inputs and all-or-none nature of spiking computations for PDN control, we explore different types of PDNs to accelerate spiking convolutional neural networks (S-CNNs) trained with the dynamic vision sensor (DVS) gesture dataset. Furthermore, we demonstrate various power gating schemes to further optimize the proposed PDN architecture, which leads to a more than a three-fold reduction in total energy overhead for spiking neural computations on systolic array-based accelerators.