Direct cache access for high bandwidth network I/O
Direct cache access for high bandwidth network I/O
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DOI：
10.1109/isca.2005.23
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发表时间：
2005-05
期刊：
影响因子：
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通讯作者：
R. Huggahalli;R. Iyer;Scott Tetrick
中科院分区：
文献类型：
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作者：
R. Huggahalli;R. Iyer;Scott Tetrick
最近的I/O技术，如PCI-Express和10gb以太网，在主流平台上实现了前所未有的I/O带宽水平。然而，在传统架构中，仅内存延迟就会限制处理器匹配10gb入站网络I/O流量。我们提出了一种平台范围的方法，称为直接缓存访问（DCA），将入站I/O数据直接传递到处理器缓存中。我们证明了DCA为接收密集型网络I/O应用程序提供了内存延迟和内存带宽的显著降低。对SPECWeb9、TPC-W和TPC-C等基准测试的分析表明，总体效益取决于I/O到内存流量的相对量，以及处理器和I/O内存访问之间的时空关系。提出了一个有效实现DCA的系统级视角。
Recent I/O technologies such as PCI-Express and 10 Gb Ethernet enable unprecedented levels of I/O bandwidths in mainstream platforms. However, in traditional architectures, memory latency alone can limit processors from matching 10 Gb inbound network I/O traffic. We propose a platform-wide method called direct cache access (DCA) to deliver inbound I/O data directly into processor caches. We demonstrate that DCA provides a significant reduction in memory latency and memory bandwidth for receive intensive network I/O applications. Analysis of benchmarks such as SPECWeb9, TPC-W and TPC-C shows that overall benefit depends on the relative volume of I/O to memory traffic as well as the spatial and temporal relationship between processor and I/O memory accesses. A system level perspective for the efficient implementation of DCA is presented.