Test and Design-for-Testability Solutions for 3D Integrated Circuits
Test and Design-for-Testability Solutions for 3D Integrated Circuits
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3D 集成电路的测试和可测试性设计解决方案
DOI：
10.2197/ipsjtsldm.7.56
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发表时间：
2014
期刊：
影响因子：
--
通讯作者：
Fangming Ye
中科院分区：
文献类型：
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作者：
K. Chakrabarty;Mukesh Agrawal;Sergej Deutsch;Brandon Noia;Ran Wang;Fangming Ye
Despite the promise and benefits offered by 3D integration, testing remains a major obstacle that hinders its widespread adoption. Test techniques and design-for-testability (DfT) solutions for 3D ICs are now being studied in the research community, and experts in industry have identified a number of hard problems related to the lack of probe access for wafers, test access in stacked dies, yield enhancement, and new defects arising from unique processing steps. We describe a number of testing and DfT challenges, and present some of the solutions being advocated for these challenges. Techniques highlighted in this paper include: (i) pre-bond testing of TSVs and die logic, including probing and non-invasive test using DfT; (ii) post-bond testing and DfT innovations related to the optimization of die wrappers, test scheduling, and access to dies and inter-die interconnects; (iii) interconnect testing in interposer-based 2.5D ICs; (iv) fault diagnosis and TSV repair; (v) cost modeling and test-flow selection.
DOI：
10.1109/ats.2011.37
发表时间：
2011-11
期刊：
2011 Asian Test Symposium
影响因子：
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作者：
Yi Zhao;S. Khursheed;B. Al-Hashimi
通讯作者：
Yi Zhao;S. Khursheed;B. Al-Hashimi