Data path placement with regularity
Data path placement with regularity
复制标题
有规律的数据路径布局
DOI：
10.1109/iccad.2000.896484
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发表时间：
2000
期刊：
影响因子：
--
通讯作者：
G. Micheli
中科院分区：
文献类型：
--
作者：
Terry Tao Ye;G. Micheli
随着越来越多的数据处理功能被集成到片上系统中，数据路径正成为整个VLSI设计的关键部分。然而，传统的物理设计方法由于不了解数据路径位片结构而不能满足数据路径性能的要求。本文提出了一种抽象物理模型（APM），用于从数据流图（DFG）中提取位片规则信息，并将其用于互连和拥塞规划。提出了一种两步启发式算法来优化APM的线性布局，以满足线路长度和路由轨迹预算。
As more data processing functions are integrated into systems-on-chip, data path is becoming a critical part of the whole VLSI design. However, traditional physical design methodology can not satisfy the data path performance requirement because it has no knowledge of the data path bit-sliced structure. In this paper, an Abstract Physical Model (APM) is proposed to extract bit-slice regularity information from Data Flow Graph (DFG) and it is used for interconnect and congestion planning. A two step heuristic algorithm is introduced to optimize the linear placement of APM to satisfy both the wire length and routing track budget.