System-Level Leakage Variability Mitigation for MPSoC Platforms Using Body-Bias Islands
System-Level Leakage Variability Mitigation for MPSoC Platforms Using Body-Bias Islands
复制标题
使用体偏置岛缓解 MPSoC 平台的系统级泄漏变异性
DOI：
10.1109/tvlsi.2011.2171512
复制
发表时间：
2012
影响因子：
2.8
通讯作者：
Diana Marculescu
中科院分区：
文献类型：
--
作者：
S. Garg;Diana Marculescu
自适应体偏置（ABB）是一种广泛使用的技术，以减轻制造工艺变化对泄漏功耗的影响。ABB技术的效率可以通过将设计划分为许多“体偏置岛”来提高，每个岛都有其单独的体偏置电压。在本文中，我们提出了一种系统级泄漏可变性缓解技术，在设计时将多处理器系统按处理元素（PE）粒度划分为体偏岛，并在制造后为每个岛分配最佳体偏电压。与先前限制系统全局时钟频率的门级和电路级分区技术相反，我们允许每个岛以不同的速度运行，并仅约束相关的系统性能指标——在我们的示例中是执行截止日期。实验结果表明了该方法的有效性；我们证明，与没有ABB的基线系统相比，泄漏功耗的平均值和标准差分别降低了40%和60%。此外，所提出的设计时间划分比先前提出的基于蒙特卡罗的技术平均快38倍，同时也提供了类似的泄漏功耗降低。
Adaptive body biasing (ABB) is a popularly used technique to mitigate the increasing impact of manufacturing process variations on leakage power dissipation. The efficacy of the ABB technique can be improved by partitioning a design into a number of “body-bias islands,” each with its individual body-bias voltage. In this paper, we propose a system-level leakage variability mitigation technique to partition a multiprocessor system into body-bias islands at the processing element (PE) granularity at design time, and to optimally assign body-bias voltages to each island post-fabrication. As opposed to prior gate- and circuit-level partitioning techniques that constrain the global clock frequency of the system, we allow each island to run at a different speed and constrain only the relevant system performance metrics - in our case the execution deadlines. Experimental results show the efficacy of the proposed methodology; we demonstrate up to 40% and 60% reduction in the mean and standard deviation of leakage power dissipation respectively, compared to a baseline system without ABB. Furthermore, the proposed design-time partitioning is, on average, 38× faster than a previously proposed Monte Carlo-based technique, while providing similar reductions in leakage power dissipation.