Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance
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DOI：
10.1145/1065579.1065718
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发表时间：
2005-06
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影响因子：
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通讯作者：
Ashish Srivastava;Saumil Shah;K. Agarwal;D. Sylvester;D. Blaauw;S. W. Director
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文献类型：
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作者：
Ashish Srivastava;Saumil Shah;K. Agarwal;D. Sylvester;D. Blaauw;S. W. Director
当前技术中工艺变化水平的增加对功率和性能具有重大影响，并导致参数良率损失。在这项工作中，我们开发了一个有效的门级方法来准确地估计参数定义的泄漏功率和延迟约束，通过寻找延迟和泄漏功率的联合概率分布函数（jpdf）的产量。我们考虑芯片间的变化，以及芯片内的变化与相关和随机组件。功率和性能之间的相关性是由于它们对常见工艺参数的依赖而产生的，并且已被证明对高频箱中的产量有显着影响。我们还提出了一种方法来估计参数产量给定的功率/延迟jpdf，这是比数值积分具有良好的精度快得多。所提出的方法被实施，并与蒙特卡洛模拟相比，显示出较高的精度，与产量估计实现的平均误差为2%。
Increasing levels of process variation in current technologies have a major impact on power and performance, and result in parametric yield loss. In this work we develop an efficient gate-level approach to accurately estimate the parametric yield defined by leakage power and delay constraints, by finding the joint probability distribution function (jpdf) for delay and leakage power. We consider inter-die variations as well as intra-die variations with correlated and random components. The correlation between power and performance arise due to their dependence on common process parameters and is shown to have a significant impact on yield in high-frequency bins. We also propose a method to estimate parametric yield given the power/delay jpdf that is much faster than numerical integration with good accuracy. The proposed approach is implemented and compared with Monte Carlo simulations and shows high accuracy, with the yield estimates achieving an average error of 2%.