A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a
A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a
复制标题
DOI：
10.1109/jssc.2007.908665
复制
发表时间：
2007-11
影响因子：
5.4
通讯作者：
J. Ryckaert;G. V. D. Plas;V. D. Heyn;C. Desset;B. V. Poucke;J. Craninckx
中科院分区：
文献类型：
--
作者：
J. Ryckaert;G. V. D. Plas;V. D. Heyn;C. Desset;B. V. Poucke;J. Craninckx
提出了一种利用脉冲无线电超宽带低占空比实现超低功耗的全数字超宽带发射机结构。该设计支持IEEE 802.15.4a标准，并演示了其强制模式。数字控制振荡器产生3到10 GHz的射频载波。它嵌入到相位对准的锁频环路中，在2 ns内启动，从而利用低至3%的信号占空比。全动态调制器按照标准的要求以499.2兆赫的码片速率以离散的步进整形BPSK符号。发射机可以工作在3.1千兆赫到10千兆赫标准的任何499.2兆赫频段，产生的信号满足发射光谱掩模。脉冲串上的抖动累积低于6 ps RMS，符合规范。该发射机采用1V90 nm数字工艺实现，1V电源的功耗在3.1 GHz时为0.65 mW，在10 GHz时为1.4 mW，数据速率为1 Mb/S。
We propose an all-digital UWB transmitter architecture that exploits the low duty cycle of impulse-radio UWB to achieve ultra-low power consumption. The design supports the IEEE 802.15.4a standard and is demonstrated for its mandatory mode. A digitally controlled oscillator produces the RF carrier between 3 and 10 GHz. It is embedded in a phase-aligned frequency-locked loop that starts up in 2 ns and thus exploits the signal duty cycle that can be as low as 3%. A fully dynamic modulator shapes the BPSK symbols in discrete steps at the 499.2 MHz chip rate as required by the standard. The transmitter can operate in any 499.2 MHz band of the standard between 3.1 and 10 GHz, and the generated signal fulfills the emission spectral mask. The jitter accumulation over a burst is below 6 psRMS, which is within specifications. The transmitter was realized in a 1 V 90 nm digital CMOS technology, and its power consumption drawn from a 1 V supply is from 0.65 mW at 3.1 GHz to 1.4 mW at 10 GHz for a 1 Mb/s data rate.