A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment
A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment
复制标题
辐照环境下单粒子效应电流源模型有线数据传输误码率测量与误差分析
DOI：
10.1007/s10836-021-05972-y
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发表时间：
2021
期刊：
影响因子：
--
通讯作者：
Kazutoshi Kobayashi
中科院分区：
文献类型：
--
作者：
Takefumi Yoshikawa;M. Ishimaru;Tatsuya Iwata;Fuma Mori;Kazutoshi Kobayashi
高速有线接口，如低电压差分信令，被广泛应用于航天领域，用于人造卫星和飞机的强大计算[19]。本文介绍了在数据发射机设计阶段对有线数据在辐照环境下传输的误码率进行预测的方法，这对于主动确定设计电路是否满足目标系统的误码率标准是有用的。使用定制设计的LVDS发送器(TX)来增强抗闭锁性能[42]，分析了晶体管尺寸与误码率之间的关系，重点分析了单粒子效应(参见)作为误码原因的情况。测量采用回旋加速器，在84Kr17+322.0 MeV、1 × 103~5 × 105计数/cm2/秒的不同注量条件下进行。为了分析比特误差，利用SPICE进行了电路仿真，用电流源模型来表示辐照环境。电流源模型表示在体MOSFET的漏极和衬底结处进入电路的单个事件冲击。为了建立电流源模型，建立了体晶体管工艺MOS器件的3D技术CAD(TCAD)模型，模拟了单粒子撞击下的电荷收集过程。将电荷修正的仿真结果转化为简单的时间域方程，并利用该方程建立了单粒子电流源模型。将单粒子电流源应用于LVDS发射机偏置电流相关电路的SPICE仿真，然后仔细验证输出数据是否受到足够大的干扰而导致有线数据传输中的误码。通过模拟，确定了敏感的MOSFET，并且与实际误码率测量结果相比，这些MOSFET的栅面积之和比通常的评价指标(漏面积之和)具有更好的相关性29%。通过使用现有模型通过SPICE模拟精确揭示敏感区域，使得在预制造设计阶段估计辐射环境下的误码率成为可能。
A high-speed wireline interfaces, e.g. LVDS (Low Voltage Differential Signaling), are widely used in the aerospace field for powerful computing in artificial satellites and aircraft [ 19 ]. This paper describes Bit Error Rate (BER) prediction methodology for wireline data transmission under irradiation environment at the design stage of data transmitter, which is useful in proactively determining if the design circuit meets the BER criteria of the target system. Using a custom-designed LVDS transmitter (TX) to enhance latch-up immunity [ 42 ], the relationship between transistor size and BER has been analyzed with focusing on Single Event Effect (SEE) as a cause of the bit error. The measurement was executed under 84 Kr 17+ exposure of 322.0 MeV at various flux condition from 1 × 10 3 to 5 × 10 5 count/cm 2 /sec using cyclotron facility. For the analysis of the bit error, circuit simulation by SPICE was utilized with expressing the irradiation environment by a current source model. The current source model represents a single event strike into the circuit at drain and substrate junctions in bulk MOSFETs. For the construction of the current source model, a charge collection was simulated at the single particle strike with the creation of 3D Technology CAD (TCAD) models for the MOS devices of bulk transistor process technology. The simulation result of the charge correction was converted to a simple time-domain equation, and the single-event current source model was produced using the equation. The single-event current source was applied to SPICE simulation at bias current related circuits in the LVDS transmitter, then simulation results are carefully verified whether the output data is disturbed enough to cause bit errors on wireline data transmission. By the simulation, sensitive MOSFETs have been specified and a sum of the gate area for these MOSFETs has 29% better correlation than the normal evaluation index (sum of the drain area) by comparison to the actual BER measurement. Through the precise revelation of the sensitive area by SPICE simulation using the current model, it became possible to estimate BER under irradiation environment at the pre-fabrication design stage.
具有可切换双模块冗余结构的抗辐射 PLL
影响因子：
0.5
作者：
SinNyoung Kim;Akira Tsuchiya;and Hidetoshi Onodera
通讯作者：
and Hidetoshi Onodera