Automated synthesis of resilient and tamper-evident analog circuits without a single point of failure
Automated synthesis of resilient and tamper-evident analog circuits without a single point of failure
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DOI：
10.1007/s10710-009-9085-2
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发表时间：
2010-03
影响因子：
2.6
通讯作者：
Kyung-Joong Kim;Adrian Wong;Hod Lipson
中科院分区：
文献类型：
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作者：
Kyung-Joong Kim;Adrian Wong;Hod Lipson
本研究的重点是使用遗传规划的鲁棒模拟电路的自动化设计。我们定义了两种互补类型的故障模式：部分短路和部分断开，并证明了新的电路，是弹性的故障水平的频谱。特别是，我们专注于设计，是一致的强大的，不像基于冗余的设计，没有任何单点故障。我们还探讨了设计防篡改电路的互补问题，这些电路对它们的操作条件的任何变化或变化都非常敏感。我们发现，组件的数量保持相似的鲁棒性和标准电路，这表明鲁棒性并不一定是在显着增加电路的复杂性。一些适应度标准，包括代理模型和协同进化被用来加速进化过程。测试了各种电路类型，并通过物理构造电路和测试其物理鲁棒性来验证所生成的解决方案的实用性。
This study focuses on the use of genetic programming to automate the design of robust analog circuits. We define two complementary types of failure modes: partial short-circuit and partial disconnect, and demonstrated novel circuits that are resilient across a spectrum of fault levels. In particular, we focus on designs that are uniformly robust, and unlike designs based on redundancy, do not have any single point of failure. We also explore the complementary problem of designing tamper-proof circuits that are highly sensitive to any change or variation in their operating conditions. We find that the number of components remains similar both for robust and standard circuits, suggesting that the robustness does not necessarily come at significant increased circuit complexity. A number of fitness criteria, including surrogate models and co-evolution were used to accelerate the evolutionary process. A variety of circuit types were tested, and the practicality of the generated solutions was verified by physically constructing the circuits and testing their physical robustness.