Design for Testability of Sleep Convention Logic
Design for Testability of Sleep Convention Logic
复制标题
睡眠约定逻辑的可测试性设计
DOI：
10.1109/tvlsi.2015.2419816
复制
发表时间：
2016
影响因子：
2.8
通讯作者：
W. Al
中科院分区：
文献类型：
--
作者：
F. A. Parsan;S. Smith;W. Al
可测试性是当今复杂的片上系统设计的主要关注点。可测性设计（DFT）技术对于任何逻辑风格都是必不可少的，包括异步逻辑风格，以降低测试成本。睡眠约定逻辑（SCL）是一种新的有前途的异步逻辑风格，它基于更知名的异步逻辑风格NULL约定逻辑（NCL）。与NCL相比，SCL目前没有可测试性方法的设计。本文的目的是分析SCL管道内的各种故障，并提出了一种基于扫描的DFT方法，使SCL可测。提出的DFT方法，然后通过大量的实验进行验证，表明该方法提供了一个高的测试覆盖率（>99%）。完整的DFT方法以及扫描链和扫描单元的设计。
Testability is a major concern in industry for today's complex system-on-chip design. Design-for-testability (DFT) techniques are essential for any logic style, including asynchronous logic styles in order to reduce the test cost. Sleep convention logic (SCL) is a new promising asynchronous logic style that is based on the more well-known asynchronous logic style NULL convention logic (NCL). In contrast to the NCL, there are currently no design for testability methodologies existing for the SCL. The aim of this paper is to analyze the various faults within SCL pipelines and propose a scan-based DFT methodology to make the SCL testable. The proposed DFT methodology is then validated through a number of experiments, showing that the methodology provides a high test coverage (>99%). The complete DFT methodology as well as the scan chain and scan cell design are presented.