Mitigating Voltage Drop in Resistive Memories by Dynamic RESET Voltage Regulation and Partition RESET
Mitigating Voltage Drop in Resistive Memories by Dynamic RESET Voltage Regulation and Partition RESET
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DOI：
10.1109/hpca47549.2020.00031
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发表时间：
2020-02
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影响因子：
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通讯作者：
Farzaneh Zokaee;Lei Jiang
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文献类型：
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作者：
Farzaneh Zokaee;Lei Jiang
新兴的电阻式随机存取存储器（ReRAM）技术因其更好的可扩展性、零单元泄漏和较短的读取延迟而被认为是主存储器中最有前途的 DRAM 替代品之一。交叉点（CP）阵列使ReRAM能够通过将单元放置在字线和位线的交叉点处来获得理论上的最小4F^2单元尺寸。然而，ReRAM CP 阵列存在较大的潜电流，导致显着的电压降，从而大大延长了阵列的 RESET 延迟。尽管先前的工作降低了 CP 阵列中的电压降，但它们要么大大增加了阵列外围设备开销，要么不能与磨损均衡方案很好地配合使用。在本文中，我们提出了两种阵列微架构级技术：动态 RESET 电压调节 (DRVR) 和分区 RESET (PR)，以减轻 ReRAM CP 阵列中位线和字线的压降。 DRVR 动态地向远离写入驱动器的单元提供较高的 RESET 电压，从而在位线上遇到较大的电压降，使得位线上的所有单元在 RESET 期间共享大致相同的延迟。 PR决定在线复位多少个单元和哪些单元，将CP阵列划分为多个具有较小字线电阻和压降的等效电路。由于DRVR和PR极大地减少了阵列RESET延迟，因此在最坏情况下不间断写入流量下基于ReRAM的主存寿命显着降低。为了提高 CP 阵列的耐用性，我们通过向字线上电压降较小的单元提供较低的 RESET 电压来进一步升级 DRVR。我们的实验结果表明，与现有压降降低技术的组合相比，我们的DRVR和PR将系统性能平均提高了11.7%，能耗平均降低了46%，同时仍然保持了>10年的主存系统寿命。
The emerging resistive random access memory (ReRAM) technology has been deemed as one of the most promising alternatives to DRAM in main memories, due to its better scalability, zero cell leakage and short read latency. The cross-point (CP) array enables ReRAM to obtain the theoretical minimum 4F^2 cell size by placing a cell at the cross-point of a word-line and a bit-line. However, ReRAM CP arrays suffer from large sneak current resulting in significant voltage drop that greatly prolongs the array RESET latency. Although prior works reduce the voltage drop in CP arrays, they either substantially increase the array peripheral overhead or cannot work well with wear leveling schemes. In this paper, we propose two array micro-architecture level techniques, dynamic RESET voltage regulation (DRVR) and partition RESET (PR), to mitigate voltage drop on both bit-lines and word-lines in ReRAM CP arrays. DRVR dynamically provides higher RESET voltage to the cells far from the write driver and thus encountering larger voltage drop on a bit-line, so that all cells on a bit-line share approximately the same latency during RESETs. PR decides how many and which cells to reset online to partition the CP array into multiple equivalent circuits with smaller word-line resistance and voltage drop. Because DRVR and PR greatly reduce the array RESET latency, the ReRAM-based main memory lifetime under the worst case non-stop write traffic significantly decreases. To increase the CP array endurance, we further upgrade DRVR by providing lower RESET voltage to the cells suffering from less voltage drop on a word-line. Our experimental results show that, compared to the combination of prior voltage drop reduction techniques, our DRVR and PR improve the system performance by 11.7% and decrease the energy consumption by 46% averagely, while still maintaining >10-year main memory system lifetime.