A 2.5ns-latency 0.39pJ/b 289μm2/Gb/s ultra-light-weight PRINCE cryptographic processor
A 2.5ns-latency 0.39pJ/b 289μm2/Gb/s ultra-light-weight PRINCE cryptographic processor
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2.5ns 延迟 0.39pJ/b 289μm2/Gb/s 超轻量 PRINCE 加密处理器
DOI：
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
J. Danger
中科院分区：
文献类型：
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作者：
N. Miura;Kohei Matsuda;M. Nagata;S. Bhasin;Ville Yli;N. Homma;Y. Mathieu;T. Graba;J. Danger
设计了一个超轻量的PRINCE密码处理器。完全展开的差分逻辑架构节省了XOR作为主要密码组件的延迟、能量和面积（即硬件权重）。一个S盒仅由四种紧凑的复合门和一个复制延迟为基础的过渡边缘对齐器组成，防止毛刺积累在长展开的组合逻辑数据路径，以进一步抑制重量。28 nm CMOS原型成功实现了2. 5 ns的延迟和0. 39 pJ/B和289μm /Gb/s的超轻量密码性能。
An ultra-light-weight PRINCE cryptographic processor is developed. A fully-unrolled differential-logic architecture saves delay, energy, and area (i.e. hardware weight) of XOR as a dominant cipher component. An S-box is composed only by four kinds of compact composite gates and a replica-delay-based transition-edge aligner prevents glitches accumulated in the long unrolled combinational-logic data path to further suppress the weight. A 28nm CMOS prototype successfully demonstrates 2.5ns-latency with 0.39pJ/b and 289μm /Gb/s of ultra-light-weight cryptographic performance.