An Approach towards Automation Firmware Modeling for an Exploration and Evaluation of Efficient Parallelization Alternatives
An Approach towards Automation Firmware Modeling for an Exploration and Evaluation of Efficient Parallelization Alternatives
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用于探索和评估高效并行化替代方案的自动化固件建模方法
DOI：
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发表时间：
2011
期刊：
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通讯作者：
J. Hartmann
中科院分区：
文献类型：
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作者：
J. Bregenzer;J. Hartmann
由于CPU周期停滞不前，如果不对多核架构进行并行化，自动化固件的未来性能增益不太可能实现。然而，对于包括数百万行代码的复杂系统，该过程引起显著的工作量，尤其是当必须保持真实的时间和安全条件时。由于效率在公司软件开发中很重要，因此希望通过不花费超过必要的实现工作来获得最大的加速。因此，并行固件的设计建议基于基于模型的探索和评估的结果，有效的并行化的替代方案。为此，我们开发了EEEPA工具链，该工具链首先基于动态事件日志进行基于图形的固件建模。
Due to stagnating CPU cycles, future performance gains in automation firmware are unlikely to be achieved without parallelization for multi-core architectures. However, for a sophisticated system comprising millions of lines of code, this process induces significant effort, especially when having to keep real time and safety conditions. As efficiency matters in corporate software development, obtaining maximum speedup by spending no more implementation effort than necessary is intended. Thus, the design of a parallel firmware is recommended to base on the results of a model-based exploration and evaluation of efficient parallelization alternatives. For this purpose, we developed the EEEPA tool chain, that starts with graph-based firmware modeling on basis of dynamic event logs.