Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device
Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device
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DOI：
10.1587/transinf.2017rcp0003
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发表时间：
2018-02
期刊：
影响因子：
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通讯作者：
T. Katashita;M. Hioki;Y. Hori;H. Koike
中科院分区：
文献类型：
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作者：
T. Katashita;M. Hioki;Y. Hori;H. Koike
摘要现场可编程门阵列器件被用于加速SPECIfic计算，并在广泛的领域中降低功耗。与ff相关的挑战之一是降低静态功率以增强其功率效率。为了降低fi器件的静态功耗，我们提出了一种基于逻辑体库和网络资源的fi细粒度侦测方法。此外，我们还利用SOTB技术开发了一款名为Flex Power的FPGA器件，并用32位计数器电路演示了其功耗降低功能。在本文中，我们描述了一个实验平台的建立，以精确地评估在各种工作电压和身体偏置下，各种实际电路的功耗和器件的最大工作频率。在上述平台上，我们使用32位加法器、16位乘法器和SBOX电路对Flex Power FPGA芯片在0.5-1.0V的工作电压和0.0-0.5V的体偏压下进行了测试。我们以统一的体偏压虚拟地操作芯片，以相同的阈值电压驱动所有的逻辑资源。通过将Flex Power现场可编程门阵列的性能与非侦察fi可编程偏置的性能进行比较，证明了Flex Power现场可编程门阵列的优势。
SUMMARY Field-programmable gate array (FPGA) devices are ap- plied for accelerating specific calculations and reducing power consumption in a wide range of areas. One of the challenges associated with FPGAs is reducing static power for enforcing their power e ff ectiveness. We propose a method involving fine-grained reconfiguration of body bi- ases of logic and net resources to reduce the static power of FPGA devices. In addition, we develop an FPGA device called Flex Power FPGA with SOTB technology and demonstrate its power reduction function with a 32-bit counter circuit. In this paper, we describe the construction of an exper- imental platform to precisely evaluate power consumption and the maximum operating frequency of the device under various operating voltages and body biases with various practical circuits. Using the abovementioned platform, we evaluate the Flex Power FPGA chip at operating voltages of 0.5–1.0 V and at body biases of 0.0–0.5 V. In the evaluation, we use a 32-bit adder, 16-bit multiplier, and an SBOX circuit for AES cryptography. We operate the chip virtually with uniformed body bias voltage to drive all of the logic resources with the same threshold voltage. We demonstrate the advantage of the Flex Power FPGA by comparing its performance with non-reconfigurable biasing.