Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System
Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System
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DOI：
10.1109/ismvl.2009.52
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发表时间：
2009-05
期刊：
影响因子：
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通讯作者：
Takashi Matsuura;H. Shirahama;M. Natsui;T. Hanyu
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文献类型：
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作者：
Takashi Matsuura;H. Shirahama;M. Natsui;T. Hanyu
提出了一种多值电流模式（MVCM）电路中的动态电流源控制技术，用于功耗敏感的流水线系统。每个流水线级中的输出监视器检测组合逻辑块已经完成了对特定输入数据的计算并且其结果已经存储到流水线寄存器中，并且产生“操作完成”信号。通过使用该控制信号来切断流水线级中的所有电流源。这种电流源控制技术的使用使得有可能完全消除浪费的稳定的电流在时钟周期的其余部分，这极大地降低了功耗与保持工作频率。在一个简单的MVCM电路中，所提出的技术的效率被确认使用90 nm CMOS下的HSPICE模拟。使用所提出的技术的MVCM电路的功耗总是小于相应的CMOS实现在0.8GHz和更高的工作频率。
A dynamic current-source control technique in multiplevalued current-mode (MVCM) circuits is proposed for a power-aware pipelined system. An output monitor in each pipeline stage detects that the combinational logic block has completed a computation for a particular piece of input data and its result has been stored into the pipeline register, and generates “operation-completion” signal. All the current sources in the pipeline stage are cut off by using this control signal. The use of this current-source control technique makes it possible to completely eliminate wasted steady current flow during the rest of clock period, which greedily reduces the power dissipation with maintaining the operating frequency. The efficiency of the proposed technique in a simple MVCM circuit is confirmed using HSPICE simulation under 90nm CMOS. The power dissipation of the MVCM circuit using the proposed technique is always less than that of a corresponding CMOS implementation at the operating frequency of 0.8GHz and more.