Design techniques for low-voltage high-speed digital bipolar circuits
Design techniques for low-voltage high-speed digital bipolar circuits
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低压高速数字双极电路设计技术
DOI：
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发表时间：
1994
期刊：
影响因子：
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通讯作者：
R. Swartz
中科院分区：
文献类型：
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作者：
B. Razavi;Y. Ota;R. Swartz
本文介绍了低至1.5V电源电压的千兆赫数字双极电路的设计技术，包括工作在1Gb/s、功耗为1.2mW的2/1多路复用器、功耗为1.4mW、最大速度为2.2GHz的D锁存器、延迟小于200 ps、功耗为1.3mW的两个异或门，以及具有165 ps的延迟同时耗散1.4 mW的缓冲器/电平移位器。原型已被制造在1.5-/spl μ/m 12 GHz的双极技术。对分频器和线路驱动器等基准电路的仿真表明，对于1.5 V电源，所提出的电路比在0.5-/SPL μ/m CMOS工艺中设计的CMOS电路实现了更高的速度，且阈值电压为零。>
This paper describes design techniques for multigigahertz digital bipolar circuits with supply voltages as low as 1.5 V. Examples include a 2/1 multiplexer operating at 1 Gb/s with 1.2 mW power dissipation, a D-latch achieving a maximum speed of 2.2 GHz while dissipating 1.4 mW, two exclusive-OR gates with a delay less than 200 ps and power dissipation of 1.3 mW, and a buffer/level shifter having a delay of 165 ps while dissipating 1.4 mW. The prototypes have been fabricated in a 1.5-/spl mu/m 12-GHz bipolar technology. Simulations on benchmarks such as frequency dividers and line drivers indicate that, for a 1.5-V supply, the proposed circuits achieve higher speed than their CMOS counterparts designed in a 0.5-/spl mu/m CMOS process with zero threshold voltage. >