VLSI implementation of a focal plane image processor - A realization of the near-sensor image processing concept
VLSI implementation of a focal plane image processor - A realization of the near-sensor image processing concept
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DOI:
10.1109/92.532033
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发表时间:
1996-09-01
影响因子:
2.8
通讯作者:
Astrom, A
中科院分区:
文献类型:
--
作者:
Eklund, JE;Svensson, C;Astrom, A
The near-sensor image processing concept, which has earlier been theoretically described, is here verified with are implementation, The NSIP describes a method to implement a two-dimensional (2-D) image sensor array with processing capacity in every pixel. Traditionally, there is a contradiction between high spatial resolution and complex processor elements, In the NSIP concept we have a nondestructive photodiode readout and we can thereby process binary images without loosing gray-scale information, The global image processing is handled by an asynchronous Global Logical Unit, These two features makes it possible to have efficient image processing in a small processor element, Electrical problems such as power consumption and fixed pattern noise are solved, All design is aimed at a 128 x 128 pixels NSIP in a 0.8 mm double-metal single-poly CMOS process, We have fabricated and measured a 32 x 32 pixels NSIP, We also give examples of image processing tasks such as gradient and maximum detection, histogram equalization, and thresholding with hysteresis. In the NSIP concept automatic light adaptivity within a 160 dB range is possible.