A 10 b 50 MS/s pipelined ADC
A 10 b 50 MS/s pipelined ADC
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10 b 50 MS/s 流水线 ADC
DOI：
10.1109/isscc.1992.200396
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发表时间：
1992
期刊：
影响因子：
--
通讯作者：
J. Verdaasdonk
中科院分区：
文献类型：
--
作者：
P. Vorenkamp;J. Verdaasdonk
到目前为止，大多数多步模数转换器（ADC）架构都受到采样和保持以及内部数模转换器（DAC）引起的线性度差的影响。此外，粗模数转换器和细模数转换器之间的增益匹配会产生非单调性。描述了一种全差分两步ADC，它提供了采样和保持，DAC，粗和细之间的增益匹配的解决方案，具有低功耗和小芯片面积的高性能
Most multistep analog-to-digital converter (ADC) architectures presented thus far suffer from poor linearity caused by the sample and hold as well as the internal digital-to-analog converter (DAC). Furthermore, the gain-matching between coarse and fine ADC gives rise to nonmonotonicity. A fully differential two-step ADC is described which presents solutions for sample and hold, the DAC, the gain-matching between coarse and fine high performance with low power consumption and small chip area.<<ETX>>