Reducing leakage in a high-performance deep-submicron instruction cache
Reducing leakage in a high-performance deep-submicron instruction cache
复制标题
减少高性能深亚微米指令缓存的泄漏
DOI：
10.1109/92.920821
复制
发表时间：
2001
期刊：
影响因子：
--
通讯作者：
T. N. Vijaykumar
中科院分区：
文献类型：
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作者：
Michael D. Powell;Se;B. Falsafi;K. Roy;T. N. Vijaykumar
深亚微米cmos设计通过降低电源电压和按比例降低晶体管阈值电压来保持较高的晶体管开关速度。降低阈值电压会增加由于亚阈值泄漏电流造成的泄漏能量消耗，即使在晶体管未切换的情况下也是如此。据估计，在未来的每一代人中，泄漏能量将增加五倍。在现代微体系结构中，大部分泄漏能量被耗散在具有高晶体管密度的大型片上高速缓冲存储器结构中。虽然高速缓存的利用率在应用内和应用之间各不相同，但现代高速缓存设计的大小是固定的，从而导致晶体管漏电效率低下。本文探索了一种集成的体系结构和电路级方法来减少指令高速缓存(I-Caches)中的泄漏能量。在体系结构层面，我们提出了可动态调整大小的I-CACHE(DRI CACHE)，这是一种新的I-CACHE设计，可以动态地调整I-CACHE的大小并适应应用所需的大小。在电路级，我们使用GATED-V/SUB dd/，这是一种新的机制，可以有效地关闭对DRI I-CACHE未使用部分中的SRAM单元的电源电压，并消除其中的泄漏。体系结构和电路级仿真结果表明，DRI I-CACHE成功且稳健地利用了缓存大小在应用程序内部和跨应用程序之间的可变性。与使用主动调整阈值电压的传统I-CACHE相比，K DRI-CACHE平均减少了62%的泄漏能量延迟乘积和CACHE大小，而对执行时间的影响不到4%。我们的结果还表明，与具有积极缩放阈值电压的I-CACHE相比，带有电荷泵的宽NMOS Dual-V/subt/Gated-V/subdd/晶体管提供了最佳的选通实现，并且在SRAM单元读取时间区域中几乎不增加泄漏能量。
Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately reducing the transistor threshold voltage. Lowering the threshold voltage increases leakage energy dissipation due to subthreshold leakage current even when the transistor is not switching. Estimates suggest a five-fold increase in leakage energy in every future generation. In modern microarchitectures, much of the leakage energy is dissipated in large on-chip cache memory structures with high transistor densities. While cache utilization varies both within and across applications, modern cache designs are fixed in size resulting in transistor leakage inefficiencies. This paper explores an integrated architectural and circuit-level approach to reducing leakage energy in instruction caches (i-caches). At the architecture level, we propose the Dynamically ResIzable i-cache (DRI i cache), a novel i-cache design that dynamically resizes and adapts to an application's required size. At the circuit-level, we use gated-V/sub dd/, a novel mechanism that effectively turns off the supply voltage to, and eliminates leakage in, the SRAM cells in a DRI i-cache's unused sections. Architectural and circuit-level simulation results indicate that a DRI i-cache successfully and robustly exploits the cache size variability both within and across applications. Compared to a conventional i-cache using an aggressively-scaled threshold voltage a 64 K DRI i-cache reduces on average both the leakage energy-delay product and cache size by 62%, with less than 4% impact on execution time. Our results also indicate that a wide NMOS dual-V/sub t/ gated-V/sub dd/ transistor with a charge pump offers the best gating implementation and virtually eliminates leakage energy with minimal increase in an SRAM cell read time area as compared to an i-cache with an aggressively-scaled threshold voltage.