A 2×25Gb/s deserializer with 2∶5 DMUX for 100Gb/s ethernet applications
A 2×25Gb/s deserializer with 2∶5 DMUX for 100Gb/s ethernet applications
复制标题
具有 2:5 DMUX 的 2×25Gb/s 解串器，适用于 100Gb/s 以太网应用
DOI：
10.1109/isscc.2010.5433827
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发表时间：
2010
期刊：
影响因子：
--
通讯作者：
Jri Lee
中科院分区：
文献类型：
--
作者：
Ke;Jri Lee
新型服务器技术（包括多核处理、虚拟化和网络存储）对带宽的需求不断增长，导致了多通道互联网连接（如100 GbE）的出现。在所提出的标准[1]中，具有4个信道的标准（例如，100 GBASE-ER 4）的选择，以达到一个合理的元件数量在离散和光子集成。本文介绍了一种双通道接收机原型，该原型能够以与全4× 25 Gb/s接收机相同的方式对数据进行放大、重定时和数字化，为全集成100 GbE收发器提供CMOS设计实例和参考。
The ever growing bandwidth requirement for novel server technologies including multi-core processing, virtualization, and networked storage leads to multichannel Internet connectivity such as 100GbE. Among the proposed standards [1], those with 4 channels (e.g., 100GBASE-ER4) are selected to arrive at a reasonable component count in discrete and photonic integration. This paper presents a 2-channel receiver prototype that amplifies, retimes, and deserializes the data in the same manner as a full 4×25Gb/s receiver, providing CMOS design examples and references for fully-integrated 100GbE transceivers.