Expandable networks for neuromorphic chips
Expandable networks for neuromorphic chips
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DOI：
10.1109/tcsi.2006.887474
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发表时间：
2007-02-01
影响因子：
5.1
通讯作者：
Boahen, Kwabena A.
中科院分区：
文献类型：
--
作者：
Merolla, Paul A.;Arthur, John V.;Boahen, Kwabena A.
我们已经开发了一个网格网络，广播尖峰（全或无事件）在多芯片神经形态系统的芯片之间的中继。网格是可扩展的，因为与总线不同，它的容量不会随着芯片的增加而减少。多个中继不会增加延迟，因为网格的周期时间比总线短。我们描述了一个异步继电器的实现，自动分配芯片地址，以指示尖峰的来源，编码为字串行地址事件。这种设计集成在每个芯片上，将神经元连接在每个芯片上的相应位置（逐点连接），并支持无意识、有针对性和排除性的尖峰传递。结果从两个芯片制造的0.25 μ m的技术，显示字速率高达45.4 M事件/s。
We have developed a grid network that broadcasts spikes (all-or-none events) in a multichip neuromorphic system by relaying them from chip to chip. The grid is expandable because, unlike a bus, its capacity does not decrease as more chips are added. The multiple relays do not increase latency because the grid's cycle time is shorter than the bus. We describe an asynchronous relay implementation that automatically assigns chip addresses to indicate the source of spikes, encoded as word-serial address-events. This design, which is integrated on each chip, connects neurons at corresponding locations on each of the chips (pointwise connectivity) and supports oblivious, targeted, and excluded delivery of spikes. Results from two chips fabricated in 0.25-mu m technology are presented, showing word-rates up to 45.4 M events/s.