Analysis of Backward Congestion Notification with Delay for Enhanced Ethernet Networks
Analysis of Backward Congestion Notification with Delay for Enhanced Ethernet Networks
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DOI：
10.1109/tc.2013.157
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发表时间：
2014-11
影响因子：
3.7
通讯作者：
Wanchun Jiang;Fengyuan Ren;Yongwei Wu;Chuang Lin;I. Stojmenovic
中科院分区：
文献类型：
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作者：
Wanchun Jiang;Fengyuan Ren;Yongwei Wu;Chuang Lin;I. Stojmenovic
目前，公司和标准组织正在增强以太网作为数据中心中所有TCP/IP流量、存储流量和高性能计算流量的统一交换结构。反向拥塞通知（BCN）是增强以太网端到端拥塞管理的基本机制。为了满足统一交换结构的特殊要求，即，由于BCN具有无丢失和低传输延迟的特点，因此BCN应该将缓冲区占用率紧紧地保持在目标点周围。因此，控制环路的稳定性和缓冲区大小对BCN至关重要。目前，延迟对BCN性能的影响尚未确定。当以太网的传输速度在不久的将来提高到40 Gbps或100 Gbps时，实时数据包的数量将与交换机的缓冲区大小保持相同的数量级。因此，延迟的影响将变得很大。在本文中，我们分析了BCN，特别注意的延迟。利用分段时滞微分方程对BCN系统进行建模，得到了BCN一致渐近稳定的充分条件。随后，缓冲区占用的界限估计，这提供了直接的指导方针设置缓冲区大小。最后，在NetFPGA平台上进行了数值分析和实验验证。
At present, companies and standards organizations are enhancing Ethernet as the unified switch fabric for all of the TCP/IP traffic, the storage traffic and the high performance computing traffic in data centers. Backward congestion notification (BCN) is the basic mechanism for the end-to-end congestion management enhancement of Ethernet. To fulfill the special requirements of the unified switch fabric, i.e., losslessness and low transmission delay, BCN should hold the buffer occupancy around a target point tightly. Thus, the stability of the control loop and the buffer size are critical to BCN. Currently, the impacts of delay on the performance of BCN are unidentified. When the speed of Ethernet increases to 40 Gbps or 100 Gbps in the near future, the number of on-the-fly packets becomes the same order with the buffer size of switch. Accordingly, the impacts of delay will become significant. In this paper, we analyze BCN, paying special attention on the delay. We model the BCN system with a set of segmented delayed differential equations, and then deduce sufficient condition for the uniformly asymptotic stability of BCN. Subsequently, the bounds of buffer occupancy are estimated, which provides direct guidelines on setting buffer size. Finally, numerical analysis and experiments on the NetFPGA platform verify our theoretical analysis.