How scaling will change processor architecture

How scaling will change processor architecture
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DOI:
10.1109/isscc.2004.1332629
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发表时间:
2004-09
期刊:
2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519)
影响因子:
--
通讯作者:
M. Horowitz;W. Dally
M. Horowitz;W. Dally
中科院分区:
其他
文献类型:
--
作者:
M. Horowitz;W. Dally

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在过去的30年中,处理器从程序员中隐藏了缩放,并显示了相同的顺序计算界面。功率和电线缩放问题导致此接口发生变化,从而暴露更多的并行性。为了提高效率,必须分发和异构机器,并将至少添加“流”编程界面。
For the past 30 years processors have hidden scaling from the programmer, presenting the same sequential computational interface. Power and wire scaling issues are causing this interface to change, exposing more parallelism. For efficiency, future machines must be distributed and heterogeneous and will add at least a "stream" programming interface.