A Six Level Gate-Driver Topology with 2.5 ns Resolution for Silicon Carbide MOSFET Active Gate Drive Development
A Six Level Gate-Driver Topology with 2.5 ns Resolution for Silicon Carbide MOSFET Active Gate Drive Development
复制标题
用于碳化硅 MOSFET 有源栅极驱动开发的分辨率为 2.5 ns 的六级栅极驱动器拓扑
DOI:
10.1109/ecce-asia49820.2021.9479081
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发表时间:
2021
期刊:
影响因子:
--
通讯作者:
S. Finney
中科院分区:
文献类型:
--
作者:
P. Judge;Ross Mathieson;S. Finney
This paper presents a new high-bandwidth multilevel gate-drive topology for use in Silicon Carbide (SiC) Active Gate-Driver Development. The presented Modular Multilevel gate Driver (MMGD) is a voltage modulated gate-driver topology that has a resolution of 2.5 ns and a current source/sink ability of approximately 5A, allowing for driving of high-power SiC MOSFETS. The MMGD is formed of off-the-shelf components, and so is readily reproducible. The speed of the gate-driver has been found to be fast enough to effectively PWM the gate of a high-power SiC MOSFET, allowing mutliple gate-driving strategies to be investigated. Experimental results using a 1.7 kV 300 A SiC MOSFET are given to validate the MMGDs ability to actively influence the switching behaviour of a high-power device.