An analytical approach to the partial scan problem
An analytical approach to the partial scan problem
复制标题
部分扫描问题的分析方法
DOI：
10.1007/bf00137392
复制
发表时间：
1990
期刊：
影响因子：
--
通讯作者：
H. Wunderlich
中科院分区：
文献类型：
--
作者：
A. Kunzmann;H. Wunderlich
扫描设计是保证时序电路可测性的最广泛使用的技术。在这篇文章中，它表明，可测性仍然是有保证的，即使只有一小部分的触发器被集成到一个扫描path.An算法，提出了选择一个最小数量的触发器，它必须是直接访问。直接的可访问性确保，对于每个故障，必要的测试序列是有界的电路尺寸线性。由于基本问题是NP完全的，高效的算法被实现来计算次优解。此外，提出了一种新的算法，将一个时序电路映射到一个最小的组合电路，这样，两种电路表示的测试向量生成是等价的，可以应用快速组合ATPG方法。对于所有的基准电路的调查，这种方法的结果在一个显着减少的硬件开销，另外一个完整的故障覆盖率仍然获得。令人惊讶的是，与完整的扫描路径相比，总的测试应用时间减少了，因为移位图案的宽度更短，并且图案的数量仅在很小程度上增加。
The scan design is the most widely used technique used to ensure the testability of sequential circuits. In this article it is shown that testability is still guaranteed, even if only a small part of the flipflops is integrated into a scan path. An algorithm is presented for selecting a minimal number of flipflops, which must be directly accessible. The direct accessibility ensures that, for each fault, the necessary test sequence is bounded linearly in the circuit size. Since the underlying problem is NP-complete, efficient heuristics are implemented to compute suboptimal solutions. Moreover, a new algorithm is presented to map a sequential circuit into a minimal combinational one, such that test pattern generation for both circuit representations is equivalent and the fast combinational ATPG methods can be applied. For all benchmark circuits investigated, this approach results in a significant reduction of the hardware overhead, and additionally a complete fault coverage is still obtained. Amazingly the overall test application time decreases in comparison with a complete scan path, since the width of the shifted patterns is shorter, and the number of patterns increase only to a small extent.