Metal Inter-layer Via Keep-out-zone in M3D IC: A Critical Process-aware Design Consideration
Metal Inter-layer Via Keep-out-zone in M3D IC: A Critical Process-aware Design Consideration
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DOI：
10.1109/isqed57927.2023.10129285
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发表时间：
2023-04
期刊：
影响因子：
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通讯作者：
M. Vemuri;Umamaheswara Rao Tida
中科院分区：
文献类型：
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作者：
M. Vemuri;Umamaheswara Rao Tida
单片三维集成电路(M3D-IC)中的金属层间通孔(MIV)用于连接层间器件，并跨多层提供电源和时钟信号。MIV的尺寸与逻辑门相当，因为顺序集成显著减少了基板层。尽管MIV的体积很小，但在M3D-IC技术中实现IC设计时，应该考虑MIV对相邻器件性能的影响。在这项工作中，我们系统地研究了晶体管放置在MIV附近时的性能变化，以了解当MIV穿过衬底时MIV对相邻器件的影响。模拟结果表明，为了保证M3DIC工艺的可靠性，必须考虑MIV的禁区(KOZ)，而KOZ高度依赖于M3DIC工艺。本文指出，当沟道掺杂为1015 cm−3，源漏掺杂为1018 cm−3，衬底高度为100 nm时，以M1金属间距为间隔放置在MIV附近的晶体管漏电流最大可增加68668倍。我们还表明，漏电流的增加也可以通过在MIV周围有Koz来显著降低，这取决于工艺。
Metal inter-layer via (MIV) in Monolithic three-dimensional integrated circuits (M3D-IC) is used to connect inter-layer devices and provide power and clock signals across multiple layers. The size of MIV is comparable to logic gates because of the significant reduction in substrate layers due to sequential integration. Despite MIV’s small size, the impact of MIV on the performance of adjacent devices should be considered to implement IC designs in M3D-IC technology. In this work, we systematically study the changes in performance of transistors when they are placed near MIV to understand the effect of MIV on adjacent devices when MIV passes through the substrate. Simulation results suggest that the keep-out-zone (KOZ) for MIV should be considered to ensure the reliability of M3DIC technology and this KOZ is highly dependent on the M3DIC process. In this paper, we show that the transistor placed near MIV considering the M1 metal pitch as the separation will have up to 68, 668× increase in leakage current, when the channel doping is 1015cm−3, source/drain doping of 1018cm−3 and substrate layer height of 100 nm. We also show that, this increase in leakage current can also be reduced significantly by having KOZ around MIV, which is dependent on the process.