A High-Performance Ramp-Voltage-Scan Winner-Take-All Circuit in an Open Loop Architecture
A High-Performance Ramp-Voltage-Scan Winner-Take-All Circuit in an Open Loop Architecture
复制标题
开环架构中的高性能斜坡电压扫描赢者通吃电路
DOI：
10.1143/jjap.41.2301
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发表时间：
2002
影响因子：
1.5
通讯作者：
T. Shibata
中科院分区：
文献类型：
--
作者：
Kiyoto Ito;M. Ogawa;T. Shibata
利用斜坡电压扫描技术，在开环结构中开发了一种快速、准确的时域赢家通吃(WTA)电路。该电路通过硬件并行计算来识别多个模拟输入电压的最小值或最大值的位置。该电路的主要特点是用一种用于时延检测的开环或树结构取代了先前工作中报告的反馈结构。结果，成功地消除了由于反馈信号延迟而导致的多赢家检测问题。测试电路采用0.6微米CMOS工艺制造，并通过测试芯片测量和版图后提取电路模拟验证了这一概念。开环或树结构电路的时间分辨率为400ps，比利用多输入或反馈信号锁存获胜者的传统WTA电路的时间分辨率高9.5倍。
A fast and accurate time-domain winner-take-all (WTA) circuit has been developed utilizing a ramp-voltage scan technique in an open loop architecture. The circuit identifies the location of the minimum or maximum value of the multiple analog input voltages by hardware parallel computation. The key feature of the circuit is the replacement of the feedback architecture reported in the previous work by an open-loop OR-tree architecture for delay detection. As a result, the problem of multiple winner detection due to the feedback signal delay has been successfully eliminated. Test circuits were fabricated in a 0.6 µm CMOS technology and the concept has been verified by test chip measurements as well as by post-layout extracted circuit simulation. The time resolution of the open-loop OR-tree architecture circuit is 400 ps, which is 9.5 times higher than that of the conventional WTA circuit utilizing a feedback signal through a multiple-input OR to latch the winner.