Low Resistive Edge Contacts to CVD‐Grown Graphene Using a CMOS Compatible Metal
Low Resistive Edge Contacts to CVD‐Grown Graphene Using a CMOS Compatible Metal
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DOI：
10.1002/andp.201600410
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发表时间：
2017-06
影响因子：
2.4
通讯作者：
M. Shaygan;M. Otto;A. Sagade;C. Chavarin;G. Bacher;W. Mertin;D. Neumaier
中科院分区：
文献类型：
--
作者：
M. Shaygan;M. Otto;A. Sagade;C. Chavarin;G. Bacher;W. Mertin;D. Neumaier
利用石墨烯的优异的固有电子性质用于器件应用受到金属和石墨烯之间的大接触电阻的阻碍。形成边缘接触而不是顶部接触是实现低欧姆接触的最有前途的解决方案之一。在本文中，大面积CVD生长的单层石墨烯的边缘接触的制造和表征，通过使用CMOS兼容的金属，即镍和铝的光学光刻的报告。通过传输线法（TLM）提取接触电阻以及使用Kelvin探针力显微镜直接测量表明，接触电阻的宽度非常低，低至130 Ωμm。发现接触电阻在高达150°C的退火温度下是稳定的，使得能够进一步进行器件处理。采用这种边缘接触的接触方案，制作了基于CVD石墨烯的场效应晶体管，在1V偏置电压下，其介电常数高达0.63mS/μm。
The exploitation of the excellent intrinsic electronic properties of graphene for device applications is hampered by a large contact resistance between the metal and graphene. The formation of edge contacts rather than top contacts is one of the most promising solutions for realizing low ohmic contacts. In this paper the fabrication and characterization of edge contacts to large area CVD‐grown monolayer graphene by means of optical lithography using CMOS compatible metals, i.e. Nickel and Aluminum is reported. Extraction of the contact resistance by Transfer Line Method (TLM) as well as the direct measurement using Kelvin Probe Force Microscopy demonstrates a very low width specific contact resistance down to 130 Ωμm. The contact resistance is found to be stable for annealing temperatures up to 150°C enabling further device processing. Using this contact scheme for edge contacts, a field effect transistor based on CVD graphene with a high transconductance of 0.63 mS/μm at 1 V bias voltage is fabricated.