Enhancing the area-efficiency of FPGAs with hard circuits using shadow clusters
Enhancing the area-efficiency of FPGAs with hard circuits using shadow clusters
复制标题
使用影子集群通过硬电路提高 FPGA 的面积效率
DOI：
10.1109/fpt.2006.270384
复制
发表时间：
2006
期刊：
影响因子：
--
通讯作者：
Jonathan Rose
中科院分区：
文献类型：
--
作者：
P. Jamieson;Jonathan Rose
FPGA和ASIC之间存在巨大的逻辑密度差距，这是FPGA在大批量应用中不具有成本效益的主要原因。现代FPGA通过包括存储器和乘法器等“硬”电路来缩小这一差距，这些电路在使用时非常有效。然而，如果不使用这些硬电路，它们就会被浪费（包括围绕逻辑的非常昂贵的可编程路由），并对逻辑密度产生负面影响。在本文中，我们提出了一个新的架构概念，称为阴影集群，旨在减轻这种损失。影子集群是一个标准的FPGA逻辑“集群”，它被放置在每个硬电路的“后面”，并且可以通过简单的小型多路复用器可编程地在不需要的情况下替换硬电路。作者测量了带和不带影子集群的FPGA的面积效率，并表明现代商业架构（具有固定的乘法器与软逻辑比率）通过采用影子集群将获得4.7%的面积效率。事实上，我们在“合理”条件下研究的每一种架构都从未显示出面积效率的损失。此外，我们表明，最有效的面积架构，采用阴影集群的概念是12.5%，比最有效的面积架构没有阴影集群
There is a dramatic logic density gap between FPGAs and ASICs, and this gap is the main reason FPGAs are not cost-effective in high volume applications. Modern FPGAs narrow this gap by including "hard" circuits such as memories and multipliers, which are very efficient when they are used. However, if these hard circuits are not used, they go wasted (including the very expensive programmable routing that surrounds the logic) and have a negative impact on logic density. In this paper we propose a new architectural concept, called shadow clusters, that seeks to mitigate this loss. A shadow cluster is a standard FPGA logic "cluster" that is placed "behind" every hard circuit and can programmably, through simple, small multiplexers, replace the hard circuit in the event it isn't needed. The authors measure the area-efficiency of FPGAs with and without shadow clusters and show that a modern commercial architecture (with a fixed ratio of multipliers to soft logic) would gain 4.7% in area-efficiency by employing shadow clusters. Indeed, every architecture we studied under "reasonable" conditions never showed a loss of area-efficiency. Furthermore, we show that most area-efficient architecture that employs the shadow cluster concept is 12.5 % better than the most area-efficient architecture without shadow clusters