Combinational Logic Design Using Six-Terminal NEM Relays
Combinational Logic Design Using Six-Terminal NEM Relays
复制标题
使用六端子 NEM 继电器的组合逻辑设计
DOI：
10.1109/tcad.2012.2232707
复制
发表时间：
2013
影响因子：
2.9
通讯作者：
S. Mitra
中科院分区：
文献类型：
--
作者：
Daesung Lee;W. S. Lee;Chen Chen;F. Fallah;J. Provine;S. Chong;J. Watkins;R. Howe;H. Wong;S. Mitra
本文介绍了纳米机电继电器为基础的逻辑电路设计技术，使用六端继电器，表现为通用逻辑门。通过适当的偏置，可以使用单个六端继电器实现紧凑的2到1多路复用器。任意组合逻辑函数可以使用众所周知的二元决策图（BDD）技术来实现。与使用四端继电器的CMOS式实现相比，基于BDD的实现可以导致更小的面积，而不会对延迟和能量等性能指标产生重大影响（当继电器缩放到小尺寸时）。虽然可以用单个机械延迟实现任何组合电路，但对于复杂的逻辑功能，通过允许多个机械延迟可以显著减少继电器数量。
This paper presents techniques for designing nanoelectromechanical relay-based logic circuits using six-terminal relays that behave as universal logic gates. With proper biasing, a compact 2-to-1 multiplexer can be implemented using a single six-terminal relay. Arbitrary combinational logic functions can then be implemented using well-known binary decision diagram (BDD) techniques. Compared to a CMOS-style implementation using four-terminal relays, the BDD-based implementation can result in lower area without major impact on performance metrics such as delay, and energy (when the relays are scaled to small dimensions). Although it is possible to implement any combinational circuit with a single mechanical delay, the relay count can be significantly reduced for complex logic functions by allowing multiple mechanical delays.