From Tensors to FPGAs: Accelerating Deep Learning-猫眼课题宝

DOI：

发表时间：

2018-08

期刊：

影响因子：

通讯作者：

中科院分区：

其他

文献类型：

作者：

Hardik Sharma;Jongse Park;Balavinayagam Samynathan;Behnam Robatmili;S. Mirkhani;H. Esmaeilzadeh

深度神经网络（DNN）是计算密集型学习模型，在视觉、机器人、视频分析、语音识别、自然语言处理、定向广告和网络搜索等广泛领域具有越来越大的适用性。随着技术扩展带来的好处越来越少，研究界越来越多地转向DNN的专业加速器。尽管ASIC为DNN提供了显著的性能和效率提升，但它们可能无法科普不断发展的DNN模型。此外，ASIC和定制内核的代价是在长设计周期内的高非经常性工程成本。FPGA是DNN的一个有吸引力的选择，因为它们代表了ASIC的效率和通用处理器的可编程性之间的中间点，并且在不同的细分市场中变得可用。然而，即使对于专业的硬件设计人员来说，使用FPGA获得性能和能效也是一项艰巨的任务。此外，DNN的大内存占用，加上FPGA有限的片上存储，使得使用FPGA的DNN加速更具挑战性。这项工作通过设计MLWEAVER（图1）来解决这些挑战，MLWEAVER是一个框架，可以从Tensorflow [1]中的高级规范自动为给定的（DNN，FPGA）对生成可合成的加速器。为了在保持自动化的同时实现巨大的效益，MLWEAVER使用手动优化的设计模板生成加速器。首先，MLWEAVER将给定的高级DNN规范转换为表示DNN的宏流图的新伊萨。MLWEAVER编译器配备了我们的优化算法，可对DNN操作进行分片、调度和批处理，以最大限度地提高数据重用率，并最佳利用目标FPGA的内存和其他资源。最终的结果是一个定制的可合成加速器，最好地匹配DNN的需求，同时为目标FPGA提供高性能和效率增益。我们使用MLWEAVER为针对三种不同FPGA（Xilinx Zynq、Altera Stratix V和Altera Arria 10）的八种不同深度网络生成加速器。我们将生成的加速器与多核CPU（ARM A15和Xeon E3）和众核GPU（Tegra K1，GTX 650Ti和Tesla K40）进行了严格的比较。表1报告了结果。这些高级DNN规范宏数据流图形加速器核心设计可合成加速器Tensorflow MLWeaver伊萨MLWeaver参数

Deep Neural Networks (DNNs) are compute-intensive learning models with growing applicability in a wide range of domains, such as vision, robotics, video analytics, speech recognition, natural language processing, targeted advertising, and web search. With diminishing benefits from technology scaling, the research community is increasingly turning to specialized accelerators for DNNs. Even though ASICs provide significant gains in performance and efficiency for DNNs, they may not cope with the ever-evolving DNN models. Furthermore, ASICs and customized cores come at the price of high non-recurring engineering costs over long design periods. FPGAs are an attractive choice for DNNs since they represent an intermediate point between the efficiency of ASICs and the programmability of general purpose processors, and are becoming available across different market segments. However, obtaining both performance and energy efficiency with FPGAs is a laborious task even for expert hardware designers. Furthermore, the large memory footprint of DNNs, coupled with the FPGAs’ limited on-chip storage makes DNN acceleration using FPGAs more challenging. This work tackles these challenges by devising MLWEAVER (Figure 1), a framework that automatically generates a synthesizable accelerator for a given (DNN, FPGA) pair from a high-level specification in Tensorflow [1]. To achieve large benefits while preserving automation, MLWEAVER generates accelerators using hand-optimized design templates. First, MLWEAVER translates a given high-level DNN specification to a novel ISA that represents a macro dataflow graph of the DNN. The MLWEAVER compiler is equipped with our optimization algorithm that tiles, schedules, and batches DNN operations to maximize data reuse and best utilize target FPGA’s memory and other resources. The final result is a custom synthesizable accelerator that best matches the needs of the DNN while providing high performance and efficiency gains for the target FPGA. We use MLWEAVER to generate accelerators for eight different deep networks targeted for three different FPGAs, Xilinx Zynq, Altera Stratix V, and Altera Arria 10. We rigorously compare the generated accelerators to multicore CPUs (ARM A15 and Xeon E3) and many-core GPUs (Tegra K1, GTX 650Ti, and Tesla K40). Table 1 reports the results. These High-Level DNN Specification Macro Dataflow Graph Accelerator Core Design Synthesizable Accelerator Tensorflow MLWeaver ISA MLWeaver Parameters

From Tensors to FPGAs: Accelerating Deep Learning

文献摘要

相似文献