The effect of interfacial traps on the stability of insulated gate devices on InP
The effect of interfacial traps on the stability of insulated gate devices on InP
复制标题
界面陷阱对InP绝缘栅器件稳定性的影响
DOI：
10.1063/1.331695
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发表时间：
1983
影响因子：
3.2
通讯作者：
M. Taylor
中科院分区：
文献类型：
--
作者：
D. Lile;M. Taylor
报告了在 InP 增强型绝缘栅场效应晶体管 (FET) 输入端施加阶跃电压后通道电流随时间变化的测量结果。数据表明，在初始稳态期之后，电流随温度呈指数变化，随时间呈对数变化。这种行为表明热激活的隧道过程是造成这些结构漂移的原因，但没有回答负责状态的起源问题。然而，尽管完全去除它可能会适得其反，但在 InP 和沉积电介质之间适当制备原生氧化物层可能对低陷阱密度界面的建立起决定性作用。
Measurements of the change in channel current with time following application of a step voltage to the input of enhancement‐mode insulated gate Field‐Effect Transistors (FETs) on InP are reported. The data indicate that, following an initial steady‐state period, the current varies exponentially with inverse temperature and logarithmically with time. This behavior suggests that a thermally activated tunneling process is responsible for the drift in these structures but leaves unanswered the question of the origin of the states responsible. It does appear, however, that, whereas its complete removal may be counterproductive, the proper preparation of the native oxide layer beween the InP and the deposited dielectric may be determinative in the establishment of a low‐trap density interface.