Self-characterization of Combinatorial Circuit Delays in FPGAs
Self-characterization of Combinatorial Circuit Delays in FPGAs
复制标题
FPGA 中组合电路延迟的自表征
DOI：
10.1109/fpt.2007.4439227
复制
发表时间：
2007
期刊：
影响因子：
--
通讯作者：
P. Cheung
中科院分区：
文献类型：
--
作者：
Justin S. J. Wong;N. P. Sedcole;P. Cheung
提出了一种内建自测试（BIST）方法来精确测量FPGA上的组合电路延迟。在现代FPGA中发现的片上时钟生成能力的灵活性被用于步进通过一系列频率，直到检测到组合电路中的定时故障。以这种方式，任何组合电路的延迟都可以用1 ps或更低的定时分辨率来确定。还提出了在FPGA上的所有LUT的延迟的自表征的方法的并行实现。该方法应用于Altera Cyclone-II FPGA（EP 2C 35）。一个完整的自我表征是在3秒内实现的，只使用13 kbit的块RAM来存储结果。这种自表征方法为匹配FPGA设计中的时序要求铺平了道路，从而解决了工艺变化问题。
This paper proposes a built-in self-test (BIST) method to measure accurately the combinatorial circuit delays on an FPGA. The flexibility of the on-chip clock generation capability found in modern FPGAs is employed to step through a range of frequencies until timing failure in the combinatorial circuit is detected. In this way, the delay of any combinatorial circuit can be determined with a timing resolution of 1 ps or lower. A parallel implementation of the method for self-characterization of the delay of all the LUTs on an FPGA is also proposed. The method was applied to an Altera Cyclone-II FPGA (EP2C35). A complete self-characterization was achieved in 3 seconds, utilizing only 13 kbit of block RAM to store the results. This self-characterization method paves the way for matching timing requirements in designs to FPGAs as a means of combating the problem of process variations.